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詹陈长

助理教授
个人简介

个人主页

詹陈长分别于2004和2007年获得上海复旦大学电子工程学士和微电子学硕士学位,于2011年获得香港科技大学电子及计算机工程博士学位。2006至2007年在上海芯原微电子有限公司担任实习模拟电路设计工程师,2011至2012年担任香港科技大学博士后研究员,2012至2014年在美国高通公司担任高级工程师, 专注于为下一代移动设备研发高性能电源管理芯片。2014年加入南方科技大学,现任深港微电子学院(国家示范性微电子学院)助理教授。詹陈长教授长期从事模拟、混合信号和电源管理集成电路与系统的分析和设计。迄今为止发表了1本专著及>60篇SCI/EI学术论文,已获授权6项中国专利、5项美国专利。詹教授获得过IEEE ISIC'2009和EDSSC'2018最佳论文奖、IEEE EDSSC'2010最佳学生论文奖、IEEE ISCAS'2011最佳学生论文奖、南方科技大学2018年度优秀青年科研奖、2019年度优秀教学奖以及优秀书院导师奖。他是IEEE APCCAS'2014的审稿委员会成员、IEEE ICTA'2018和ICTA'2019的技术程序委员会成员、 Hindawi APEC期刊客座编辑、IEEE ISCAS'2018, ISCAS'2019以及 ICTA'2018的分会场主席/共同主席,同时他还担任集成电路领域众多国际知名期刊和会议的特邀审稿人。他是IEEE高级会员。
教育经历

2007-2011 香港科技大学电子及计算机工程学,博士

2004-2007 复旦大学微电子学及固体电子学,硕士
2000-2004 复旦大学电子信息科学与技术,学士

工作经历

2014至今 南方科技大学,助理教授
2012-2014 美国高通公司,高级工程师
2011-2012 香港科技大学,博士后研究员

研究简介

电源管理、能量收集集成电路与系统
模拟与混合信号集成电路
低功耗集成电路设计方法
ResearcherID链接: https://publons.com/researcher/1807217/chenchang-zhan/
Google Scholar链接: https://scholar.google.com/citations?user=tYZ863gAAAAJ&hl=en

所获荣誉

2019,获晋升为IEEE Senior Member
2019,南方科技大学“优秀教学奖”
2019,南方科技大学“优秀书院导师奖”
2018,南方科技大学“优秀青年科研奖”
2018,IEEE EDSSC最佳论文奖
2017,南方科技大学首届创新创业大赛“优秀导师”
2016,第六届全国大学生集成电路设计大赛“优秀指导教师”
2016,南方科技大学“招生工作先进个人”
2016,南方科技大学树仁书院“年度导师”
2016,广东省深圳市南山区“领航人才”C类
2014,广东省深圳市海外高层次“孔雀计划”人才C类
2011,IEEE ISCAS最佳学生论文奖
2010,IEEE EDSSC最佳学生论文奖
2009,IEEE ISIC最佳论文奖
2009,IEEE ISCAS最佳论文奖提名

代表文章

J. Lin, L. Wang, C. Zhan and Y. Lu, "A 1-nW Ultra-Low Voltage High PSRR Subthreshold CMOS Voltage Reference with 0.0154%/V Line Sensitivity," IEEE Trans. Circ. Syst. II: Exp. Briefs, vol. 66, no.10, pp. 1653-1657, Oct. 2019. https://doi.org/10.1109/TCSII.2019.2920693.

G. Cai, C. Zhan and Y. Lu, “A fast-transient-response fully-integrated digital LDO with adaptive current step size control,” IEEE Tran. Circ. Syst. I: Reg. Papers, vol. 66, no. 9, pp. 3610-3619, Sept. 2019. https://doi.org/10.1109/TCSI.2019.2917558.

L. Wang and C. Zhan, “A 0.7-V 28-nW CMOS subthreshold voltage and current reference in one simple circuit,” IEEE Tran. Circ. Syst. I: Reg. Papers, vol. 66, no. 9, pp. 3457-3466, Sept. 2019. https://doi.org/10.1109/TCSI.2019.2927240.

Y. Tan, C. Zhan and G. Wang, "A fully-on-chip analog low-dropout regulator with negative charge pump for low-voltage applications," IEEE Trans. Circ. Syst. II: Exp. Briefs, vol. 66, no. 8, pp. 1361-1365, Aug. 2019. https://doi.org/10.1109/TCSII.2018.2881072.

C. Zhan, G. Cai and W. H. Ki, “A transient-enhanced output-capacitor-free low-dropout regulator with dynamic miller compensation,” IEEE Trans. On Very Large Scale Integration (VLSI) Systems, vol. 27, no. 1, pp. 243-247, Jan. 2019. https://doi.org/10.1109/TVLSI.2018.2867850.

H. Li, C. Zhan and N. Zhang, "A fully-on-chip digitally assisted LDO regulator with improved regulation and transient responses," IEEE Tran. Circ. Syst. I: Reg. Papers, vol. 65, no. 11, pp. 4027-4034, Nov. 2018. https://doi.org/10.1109/TCSI.2018.2851514.

Q. Huang, C. Zhan, and J. Burm, “A 30 MHz Voltage-Mode Buck Converter Using Delay-Line-Based PWM Control,” IEEE Trans. Circ. Syst. II: Exp. Briefs, vol. 65, no. 11, pp. 1659-1663, Nov. 2018. https://doi.org/10.1109/TCSII.2017.2764048.

L. Wang, C. Zhan, J. Tang, Y. Liu and G. Li, “A 0.9V 33.7ppm/ºC 85nW sub-bandgap voltage reference consisting of subthreshold MOSFETs and single BJT,” IEEE Trans. On Very Large Scale Integration (VLSI) Systems, vol. 26, no. 10, pp. 2190-2194, Oct. 2018. https://doi.org/10.1109/TVLSI.2018.2836331.

C. Huang, C. Zhan, L. He, L. Wang and Y. Nan, "A 0.6V-minimum-supply, 23.5ppm/ºC subthreshold CMOS voltage reference with 0.45% variation coefficient," IEEE Trans. Circ. Syst. II: Exp. Briefs, vol. 65, no. 10, pp. 1290-1294, Oct. 2018. https://doi.org/10.1109/TCSII.2018.2846808.

Y. Liu, C. Zhan, L. Wang, J. Tang and G. Wang, “A 0.4-V wide temperature range all-MOSFET subthreshold voltage reference with 0.027%/V line sensitivity,” IEEE Trans. Circ. Syst. II: Exp. Briefs, vol. 65, no. 8, pp. 969-973, Aug. 2018. https://doi.org/10.1109/TCSII.2018.2794512.

L. Wang, C. Zhan, J. Tang and G. Li, “An amplifier-offset-insensitive and high PSRR subthreshold CMOS voltage reference.” Int’l J. Circ. Theor. Appl., vol. 46, no. 2, pp. 259-271, Feb. 2018. https://doi.org/10.1002/cta.2383.

S. Zhao, C. Zhan and G. Cai, “A 2×VDD-enabled output-capacitor-free low-dropout regulator with fast transient response for low-cost system-on-chip,” J. Circ. Syst. Comp., vol. 27, no.9, pp. 1850143-1-17, Jan. 2018. https://doi.org/10.1142/S0218126618501438.

Y. Liu, C. Zhan and L. Wang, “An ultralow power subthreshold CMOS voltage reference without requiring resistors or BJTs,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 26, no. 1, pp. 201-205, Jan. 2018. https://doi.org/10.1109/TVLSI.2017.2754442.

Q. Huang, C. Zhan and J. Burm, “A low-complexity locking-accelerated digital PLL with multi-output bang-bang phase detector,” Microelectronics Journal, vol. 67, pp. 19-24, Sept. 2017. https://doi.org/10.1016/j.mejo.2017.07.004.

L. Wang, C. Zhan, J. Tang, S. Zhao, G. Cai, Y. Liu, Q. Huang and G. Li, “Analysis and design of a current-mode bandgap reference with high power supply ripple rejection,” Microelectronics Journal, vol. 68, pp. 7-13, Aug. 2017. https://doi.org/10.1016/j.mejo.2017.08.011.

Q. Huang, H. Joo, J. Kim, C. Zhan and J. Burm, “An energy-efficient frequency domain CMOS temperature sensor with switched Vernier time-to-digital conversion,” IEEE Sensors Journal, vol. 17, no. 10, pp. 3001-3011, May 2017. https://doi.org/10.1109/JSEN.2017.2686442.

C. Zhan and W. H. Ki, “Analysis and design of output-capacitor-free low-dropout regulators with low quiescent current and high power supply rejection,” IEEE Tran. Circ. Syst. I: Reg. Papers, vol. 61, no. 2, pp. 625-636, Feb. 2014 (Top 5 most frequently downloaded paper in Feb. 2014). https://doi.org/10.1109/TCSI.2014.2300847.

C. Zhan and W. H. Ki, “An output-capacitor-free adaptively biased low-dropout regulator with subthreshold undershoot-reduction for SoC,” IEEE Tran. Circ. Syst. I: Reg. Papers, vol. 59, no. 5, pp. 1119-1131, May 2012 (Invited to Special Issue on ISCAS 2011). https://doi.org/10.1109/TCSI.2012.2190675.

W. H. Ki, K. M. Lai and C. Zhan, “Charge balance analysis and state transition analysis of hysteretic voltage mode switching converters,” IEEE Tran. Circ. Syst. I: Reg. Papers, vol. 58, no.5, pp. 1142-1153, May 2011. https://doi.org/10.1109/TCSI.2010.2089557.

C. Zhan and W. H. Ki, “A Low dropout regulator with low quiescent current and high power supply rejection over wide range of frequency for SoC,” J. Circ. Syst. Comp., vol. 20, no. 1, pp. 1-13, Jan. 2011 (Invited to Special Issue on Green Integrated Circuits). https://doi.org/10.1142/S0218126611007037.

C. Zhan and W. H. Ki, “Output-capacitor-free adaptively biased low-dropout regulator for system-on-chips,” IEEE Tran. Circ. Syst. I: Reg. Papers, vol. 57, no. 5, pp. 1017-1028, May 2010 (Invited to Special Issue on ISCAS 2009). https://doi.org/10.1109/TCSI.2010.2046204.

C. Zhan, X. Zhou, and D. Zhou, “A low-power high-resolution sigma-delta modulator,” Research & Progress of Solid-State Electronics, vol. 27, no. 3, pp. 375-379, Aug. 2007. https://doi.org/10.3969/j.issn.1000-3819.2007.03.021

C. Zhan, Y. Wang, X. Zhou, H. Min and D. Zhou, “A deep-submicron sigma-delta ADC design flow,” Research & Progress of Solid-State Electronics, vol. 27, no. 1, pp. 63-68, Feb. 2007. https://doi.org/10.3969/j.issn.1000-3819.2007.01.014