2014 Ph.D. Department of Electrical and Computer Engineering, the Hong Kong University of Science and Technology
2005 B.S. Department of Electrical Engineering, University of Science and Technology of China

2022-present, Associate Professor, Southern University of Science and Technology
2011-2022, Assistant Professor, Southern University of Science and Technology

Optical communication integrated circuits
Silicon Photonic Interconnects
Serdes/CDR
Analog/RF integrated circuits

Outstanding Young Author Award, IEEE Circuits and Systems Society, 2017.
Innovation Prize Winner, the 4th Annual HKUST One Million Dollar Entrepreneurship Competition, 2014.

J. Wang, Q. Pan* et al., "A Fully-Integrated 25Gb/s Low-Noise TIA+CDR Optical Receiver Designed in 40nm-CMOS," TCAS-II, DOI 10.1109/TCSII.2019.2925363, Jun. 2019.
Q. Pan et al., “A 42-dBΩ 25-Gb/s CMOS Transimpedance Amplifier with Multiple-Peaking Scheme for Optical Communications,” IEEE Transactions on Circuits and Systems II: Express Briefs, Feb. 2019.
Y. Guo, and Q. Pan, “A PAM-4 80-Gb/S Variable-Gain Transimpedance Amplifier in 40-nm CMOS Technology,” in IEEE International Conference on Integrated Circuits, Technologies and Applications, Nov. 2018.
Q. Pan, Y. Wang, Z. Hou, L. Sun, L. Wu, W. H. Ki, P. Chiang, and C. P. Yue, “A 41-mW 30-Gb/s CMOS Optical Receiver with Digitally-Tunable Cascaded Equalization,” in Proc. European Solid-State Circuits Conf., Sep. 2014.
Q. Pan, Z. Hou, Y. Wang, Y. Lu, W. H. Ki, K. C. Wang, and C. P. Yue, “A 48-mW 18-Gb/s Fully Integrated CMOS Optical Receiver with Photodetector and Adaptive Equalizer,” in Symp. VLSI Circuits Dig. Tech. Papers, pp. 116−117, Jun. 2014.
Q. Pan, Z. Hou, Y. Li, A. W. Poon, and C. P. Yue, “A 0.5-V P-Well/Deep N-Well photodetector in 65-nm CMOS for monolithic 850-nm optical receivers,” IEEE Photonics Technology Letters (PTL), vol. 26, no. 12, pp. 1184−1187, Jun. 2014.
Q. Pan, T. J. Yeh, C. Jou, F. L. Hsueh, H. Luong, and C. P. Yue, “A performance study of layout and Vt options for low noise amplifier design in 65-nm CMOS,” in IEEE Radio Frequency Integrated Circuits Symp., pp. 535−538, Jun. 2012.
G. Zhu, Q. Pan, J. Zhuang, C. Zhi, and C. P. Yue, “A Low-Power PAM4 Receiver Using 1/4-Rate Sampling Decoder with Adaptive Variable-Gain Rectification,” in 2017 IEEE Asian Solid-State Circuits Conf., Nov. 2017.
Y. Wang, D. Luo, Q. Pan, L. Jing, Z. Li, and C. P. Yue, “A 60-GHz 4-Gb/s Fully Integrated NRZ-to-QPSK Fiber-Wireless Modulator,” IEEE Transactions of Circuits and Systems−I (TCAS-I), vol. 64, issue. 3, pp. 653−663, Mar. 2017.
L. Sun, Q. Pan, K. C. Wang, and C. P. Yue, “A 26-28-Gb/s clock and data recovery circuit with embedded equalizer in 65-nm CMOS,” IEEE Transactions of Circuits and Systems−I (TCAS-I), vol. 61, no. 7, pp. 2139−2149, Jul. 2014.