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YU Hao

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Professor Hao Yu is currently Vice Dean and Tenured Professor at the School of Microelectronics, Southern University of Science and Technology (SUSTech), China. He also serves as Director of the MOE Engineering Research Center for Future Communication Integrated Circuits, and Head of the SUSTech–ARM China / ZTE AI Joint Laboratory. He received his bachelor’s degree from Fudan University and his PhD in Electrical Engineering from the University of California, Los Angeles (UCLA). Prior to joining SUSTech, he was an Assistant Professor and Director of the Integrated Circuits Research Center at Nanyang Technological University, Singapore. His research focuses on advancing artificial intelligence through hardware, algorithm and system-level innovation.
Professor Yu has more than 30-year experience in high-performance integrated circuit design. His research interests include 3D-IC, in-memory computing, and embodied AI. His work is characterized by a strong emphasis on algorithm–architecture–circuit co-design, enabling efficient, scalable, and deployable AI systems for real-world applications in intelligent computing, robotics, communications, and biomedical sensing.
Professor Yu has been recognized by several prestigious national talent programs, as well as notably the Wu Wenjun Artificial Intelligence Technology Invention Award (2019) and the Wu Wenjun AI Chip Special Award (2020). He has served as Editor or Associate Editor for multiple IEEE/ACM/Elsevier journals and held leadership roles in major international conference.
Professor Yu has published 340+ papers, including IEEE/ACM journal articles and international conference papers. His research outcomes have received Best Paper Awards from major international conferences and organizations such as IEEE-ICARM, IEEE-RAS (World Robot Conference), IEEE-BioCAS, ACM TODAES, and SRC. These works span AI chips, intelligent robotics, and AI-driven bioelectronics. His research has been supported by significant national and regional funding programs as well as industries.

Educational Background

2002 – 2007 University of California at Los Angeles Los Angeles (CA, USA)
Degree: M.S. (2005)/Ph. D. (2007) Electrical Engineering
Major: Integrated circuit and embedded computing system
Research Work: High-speed and high frequency RF and interconnect circuit design
1994 – 1999 Fudan University (Shanghai, China)
Degree: B. S. with honors in physics (Solid-State)
Research Work: Non-equilibrium transport phenomena in nano-scale semiconductor devices

Professional Experience

2019/01-present Southern University of Technology and Science (SUSTech, Shenzhen China)
Professor: School of Microelectronics
2017/06-2018/12 Southern University of Technology and Science (SUSTech, Shenzhen China)
Associate Professor: Department of Electrical and Electronic Engineering
2010–2017 Nanyang Technological University (Singapore)
Assistant Professor: School of Electrical and Electronic Engineering
Program Director of VIRTUS IC Design Center of Excellence since 2010
Program Director of VALENS Biomedical Center of Excellence since 2014
Cluster Director of Energy Research Institute @ NTU since 2016 since 2016

Research Interests

CMOS Emerging Technology for Data Sensing, Links and Analytics, High-speed 3D-IC and THz interconnect, Energy-efficient data analytics accelerator (CNN/BNN/TNN machine learning SoC), Smart multi-modal (pH, image, THz) sensor for personalized biomedical diagnosis.

Honors & Awards

Outstanding Paper Award at IEEE Advanced Robotics and Mechatronics Conference(2022)
Best Student Paper Award at IEEE Advanced Robotics and Automation WRC Symposium (2021)
10th WU Wen-Jun AI Science & Technology Award for AI Chip (2020
9th WU Wen-Jun AI Science & Technology Award for Technology Invention (2019)
Invention Award at Chinese Industry- Academia-Research Cooperation (2018)
Best Paper Award at IEEE Biomedical Circuits and Systems Conference (2018)
Distinguished Lecturer of IEEE Circuits and Systems Society (2017-20219)
Best Paper Award at ACM Trans. on Design Automation of Electronic Systems (2010)
Inventor Award at Semiconductor Research Cooperation (SRC) (2009)

Selected Publication

Selected Journal Publications
J120. (TCAS1’26) Yichen Ouyang, Zhentao Zheng, Runsen Zhang, Zhenyu Su, Lei Chen, Hao Yu, Fengwei An, "A UHD@60fpsPerceptual Texture-Aware Local DimmingProcessor for Mini-LED HDR Displays," IEEE Transactions on Circuits and Systems I: Regular Papers, June 2026.
J119. (ICS’26) Sixiao Huang, Xu Shi, Mingqiang Huang, and Hao Yu, "A Neural Architecture Search Optimized Mixed-Precision Systolic-in-Systolic DNN Accelerator on FPGA," IEEE Integrated Circuits and Systems, June 2026.
J118. (TVLSI’26) Quan Cheng, Longyang Lin, Mingqiang Huang, Qiufeng Li, Zhengke Yang, Liuyao Dai, Hao Yu, Ruilin Zhang, Yu-Jen Chen, Yiyu Shi, Masanori Hashimoto, "A 22nm End-to-End Edge- AI Processor with Booth-Value-Confined Acceleration and Hardware-Aware Layer-Wise Model Deployment," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, June 2026.
J117. (TCAD’26) Ziyi Guan#, Zhengfei Chen#, Dongkuan Wu, Ao Shen, Yifan Guo, Yupeng Su, Graziano Chesi, Mingqiang Huang, Ngai Wong, and Hao Yu*, "APTQ+: Attention-FFN-aware Post-Training Quantization for a Layer-wise LLM Accelerator on FPGA," IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, May 2026
J116. (OPT’25) Zhengqi Li, Yumeng Luo, Zhenyu Liu, Xingyu Tang, Yingxin Li, Ning Ding, Mingjian You, Min Wang, Quan Pan, Kwai Hei Li, Hao Yu*, and Qiancheng Zhao*, "Fast-response infrared photodetector based on PbS quantum dots for integrated photonic devices characterization," Optics Express, vol.33, no.25, pp.52839-52851, Dec 2025.(doi:10.1364/OE.581982)
J115. (JSSC’25) Kai Li, Mingqiang Huang, Ang Li, Shuxin Yang, Quan Cheng, Hao Yu*, "A 29.12 TOPS/WVector Systolic Accelerator with NASoptimized DNNs in 28-nm CMoS", IEEE Journal of Solid-State Circuits (JSSC), pp.1-12, April 2025.(doi:10.1109JSSC.2025.3558287)
J114. (TPAMI’25) Hongwei Ren, Yue Zhou, Jiadong Zhu, Xiaopeng Lin, Haotian Fu, Yulong Huang, Yuetong Fang, Fei Ma, Hao Yu and Bojun Cheng, "Rethinking Efficient and Effective point-based Networks for Event Camera Classification and Regression", IEEE Transactions on Pattern Analysis and Machine Intelligence, pp.1-14, March 2025.(doi:10.1109/TPAMI.2025.3556561)
J113. (TCAS1’25) Mingqiang Huang, Ao Shen, Kai Li, Haoxiang Peng, Boyu Li, Yupeng Su, Hao Yu*, “EdgeLLM: A Highly Efficient CPU-FPGA Heterogeneous Edge Accelerator for Large Language Models” , IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 72, no. 7, pp.3352 - 3365, July 2025. (doi:10.1109/TCSI.2025.3546256).
J112. (ICS’25) Shaobo Luo, Albert Yu, Zhiyuan Xie, Hong Huang, Mingqiang Huang, Kai Li, Yuk Kan Pun, Zhiru Guo, Shuwei Li, Yiming Zhu, Changhai Man, Huiyuan Sun, Tung-Han Chang, Ziyi Guan, Qiyuan Zhang, Tingting Wang, Guanqi Peng, Wenjun Chen, Yan Sun3, Gengxin Chen, Mei Yan*, Hao Yu*, "emGene: An Embodied LLM NGS Sequencer for Real-time Precision Diagnostics", IEEE Integrated Circuits and Systems, pp.1-15, March 2025. (doi:10.23919/ICS.2025.3552542).
J111. (JSEN’25) Jin Chen, Liangzun Fu, Rikui Xiang, Shaobo Luo, Xiwei Huang, Hao Yu, Lingling Sun, "Artificial Intelligence-assisted Microfluidic Bio-imaging -from Sensors to Applications:A Review," IEEE Sensors Journal, pp.1-1, Dec.05, 2024. (doi: 10.1109/JSEN.2024.3507081).
J110. (TCAS1’24) Wei Mao, Dingbang Liu, Haoxiang Zhou, Fuyi Li, Kai Li, Qiuping Wu, Jiaqi Yang, Quan Cheng, Liuyang Zhang and Hao Yu, “A 28-nm 135.19 TOPS/W Bootstrapped-SRAM Compute-in-Memory Accelerator with Layer-wise Precision and Sparsity”, IEEE Transactions on Circuits and Systems I: Regular Papers, 2024. (Accepted)
J109. (TCAS2’24) Wei Mao, Fuyi Li, Jun Liu, Rui Xiao, Kejie Huang, Yongfu Li, Hao Yu, Yan Liu and Genquan Han, “A Low-Power Charge-Domain Bit-Scalable Readout System for Fully-Parallel Computing-in-Memory Accelerators”, IEEE Transactions on Circuits and Systems Il, vol. 71, no. 6, pp. 2916-2920, June 2024. (doi: 10.1109/TCSII.2023.3330080).
J108. (TCAS2’24) Boyu Li, Kai Li, Jiajun Zhou, Yuan Ren, Wei Mao, Hao Yu and Ngai Wong, “A Reconfigurable Processing Element for Multiple-Precision Floating/Fixed-Point HPC”, IEEE Transactions on Circuits and Systems Il, vol. 71, no. 3, pp. 1401-1405, March 2024. (doi: 10.1109/TCSII.2023.3322259).
J107. (OJCAS’24)Laimin Du, Leibin Ni, Xiong Liu, Guanqi Peng, Kai Li, Wei Mao* and Hao Yu*, “A Low-Power DNN Accelerator with Mean Error Minimized Approximate Signed Multiplier,” IEEE Open Journal of Circuits and Systems, vol. 5, pp. 57-68, 2024.(doi: 10.1109/OJCAS.2023.3279251)

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