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CHEN Quan

Assistant Professor
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Dr. Chen Quan is an Assistant Professor at the School of Microelectronics, Southern University of Science and Technology (SUSTech), and a PhD supervisor. A recognized high-level overseas talent in Shenzhen, he earned his PhD from the University of Hong Kong and previously held positions at UC San Diego and the University of Hong Kong.

Dr. Chen’s research focuses on advanced algorithms and tools in electronic design automation (EDA), particularly in large-scale analog and RF circuit simulation, multi-physics analysis, and nanodevice simulation. He has published over 50 papers in top EDA journals and conferences (TCAD, DAC, ICCAD), holds four Chinese patents, and has received several honors, including the Wu Wenjun Artificial Intelligence Chip Award and an ICCAD Best Paper Award nomination.

He has led and participated in numerous major research projects, including key, general, and special projects under the National Natural Science Foundation of China (NSFC), as well as major R&D project for Guangdong Province. He also leads several industry collaboration projects with EDA giants such as Huawei, Empyrean, and Guowei Group.

Dr. Chen welcomes individuals passionate in EDA research to join his research group. He has openings for Postdoctoral Fellows, Research Assistants, Graduate Students, as well as Internships. Interested individuals are invited to email a copy of his/her CV to his email address.
Contact：chenq3@sustech.edu.cn

Educational Background

2010, Ph.D., The University of Hong Kong
2007, Master, The University of Hong Kong
2005, Bachelor, Sun Yat-Sen (Zhongshan) University

Professional Experience

Apr. 2019 to present, Assistant Professor, Southern University of Science and Technology,
Nov. 2012 to Dec, 2018, Research Assistant Professor, The University of Hong Kong (HKU)
Dec. 2011 to Oct. 2012, Postdoctoral Fellow, The University of Hong Kong (HKU)
Oct. 2010 to Nov. 2011, Postdoctoral Fellow, University of California, San Diego (UCSD)

Research Interests

Large-scale advanced analog/RF circuit simulation methods
Post-Moore era multi-physics analysis techniques
AI-assisted EDA technologies

Honors & Awards

2020 Wu Wenjun Artificial Intelligence Science and Technology Award, Second Prize
ICCAD 2012 Best Paper Award Nomination

Selected Publication

Journal paper:
1.L. Ouyang, C. Jin and Q. Chen, "A Recycling Krylov Subspace Method With High-Order Time Integration Methods for Fast Periodic AC and Noise Analysis," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 71, no. 9, pp. 4180-4188, Sept. 2024, doi: 10.1109/TCSI.2024.3410384. 
2.L. Ouyang, C. Jin and Q. Chen, "A Fast Recycling GMRES Method With Smart Frequency Sweeping for Efficient Periodic Small-Signal Analysis," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no. 8, pp. 3765-3769, Aug. 2024, doi: 10.1109/TCSII.2024.3372404
3.Tao, Chaofan; Lin, Rui; Q. Chen; Zhang, Zhaoyang; Luo, Ping; Wong, Ngai, “FAT: Frequency-Aware Transformation for Bridging Full-Precision and Low-Precision Deep Representations”, IEEE Transactions on Neural Networks and Learning Systems, vol. 35, no. 2, pp. 2640 - 2654, Feb.2024
4.Yao Tong; Q. Chen, “Analytical Modeling of Multiple Co-Existing Inaccuracies in RF Controlling Circuits for Superconducting Quantum Computing”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 43, no. 1, pp. 319 - 323, Jan.2024
5.Cong Wang; Dongen Yang; Jinming Lyu; Yong Dai; Cheng Zhuo; Q. Chen, “On Model Order Reduction and Exponential Integrator for Transient Circuit Simulation”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 43, no. 1, pp. 328 - 339, Jan.2024
6.T. Hou, N. Wong, Q. Chen, Z. Ji and H. -B. Chen, Analytical Post-Voiding Modeling and Efficient Characterization of EM Failure Effects Under Time-Dependent Current Stressing," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, no. 12, pp. 4959-4972, Dec. 2023.
7.Tianshu Hou; Peining Zhen; Ngai Wong; Q. Chen; Guoyong Shi; Shuqi Wang; Hai-Bao Chen,“Multilayer Perceptron-Based Stress Evolution Analysis Under DC Current Stressing for Multisegment Wires," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, no. 2, pp. 544-557, Feb. 2023
8.D. Liu and Q. Chen, "TEMT: A Transient Electronic–Magnetic–Thermal-Coupled Simulation Framework for STT-MTJs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, no. 5, pp. 1623-1633, May 2023.
9.Dingbang Liu; Haoxiang Zhou; Wei Mao; Jun Liu; Yuliang Han; Changhai Man; Qiuping Wu; Zhiru Guo; Mingqiang Huang; Shaobo Luo; Mingsong Lv; Q. Chen; Hao Yu, "An Energy-Efficient Mixed-Bit CNN Accelerator With Column Parallel Readout for ReRAM-Based In-Memory Computing," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 12, no. 4, pp. 821-834, Dec. 2022.
10.Tianshu Hou; Ngai Wong; Q. Chen; Zhigang Ji; Hai-Bao Chen, “A Space-Time Neural Network for Analysis of Stress Evolution under DC Current Stressing”,IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 12, pp. 5501-5514, Dec. 2022.
11.Q. Chen, “EI-NK: A Robust Exponential Integrator Method with Singularity Removal and Newton-Raphson Iterations for Transient Nonlinear Circuit Simulation”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems，vol. 41, no. 6, pp. 1693-1703, June 2022

Conference paper:
7.H. Zhou and Q. Chen, “EI-PIT: A Parallel-in-Time Exponential Integrator Method for Transient Linear Circuit Simulation”, 2024 IEEE/ACM International Conference On Computer Aided Design (ICCAD), USA, Oct. 2024.
8.H. Zhou, D. Yang, Y. Lin, Y. Dai and Q. Chen, "A Parallel Acceleration Technique based on Bordered Block Diagonal Matrix Reordering for Exponential Integrator Method," 2024 2nd International Symposium of Electronics Design Automation (ISEDA), Xi'an, China, 2024, pp. 94-99, doi: 10.1109/ISEDA62518.2024.10617631.
9.Geng Bai, Jinming Lyu, Yangfei Lin, Xingming Liu, Yong Dai, Dongen Yang, Lingyun Ouyang, Cong Wang, Q. Chen, "Back-Scaling Based Exponential Integrator Method with Multi-Process Parallel Processing for Transient Power/Ground Network Analysis," 2023 International Symposium of Electronics Design Automation (ISEDA), Nanjing, China, May 2023.
10.Y. Sha, J. Lan, Y. Li and Q. Chen, "A Physics-Informed Recurrent Neural Network for RRAM Modeling," 2023 International Symposium of Electronics Design Automation (ISEDA), Nanjing, China, May 2023.
11.C. Wang, D. Yang and Q. Chen, "EI-MOR: A Hybrid Exponential Integrator and Model Order Reduction Approach for Transient Power/Ground Network Analysis," 2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD), San Diego, CA, USA, Oct. 2022.
12.Q. Chen, “A Robust Exponential Integrator Method for Generic Nonlinear Circuit Simulation”, Design Automation Conference (DAC), San Francisco, Jul. 2020.

ZHANG Guobiao
YU Hongyu